Transistors are key components of modern integrated circuits. To satisfy the requirements of increasingly faster speed, the drive currents of transistors need to be increasingly greater. Since the drive currents of transistors are proportional to gate widths of the transistors, transistors with greater widths are preferred.
The increase in gate widths, however, conflicts with the requirements of reducing sizes of semiconductor devices. Fin field-effect transistors (FinFET) are thus formed. FIG. 1 illustrates a perspective view of a conventional FinFET. Fin 4 is formed as a vertical silicon fin extending above substrate 2, and is used to form source and drain regions 6 and a channel region therebetween (not shown). A vertical gate 8 intersects the channel region of fin 4. While not shown in FIG. 1, a gate dielectric separates the channel region from vertical gate 8. FIG. 1 also illustrates oxide layer 18, and insulating sidewall spacers 12 and 14 formed on source and drain regions 6 and vertical gate 8, respectively. The ends of fin 4 receive source and drain doping implants that make these portions of fin 4 conductive.
Typically, a semiconductor chip contains a plurality of FinFETs. Problems arise when FinFETs are formed adjacent to each other. FIG. 2 illustrates a cross-sectional view of an intermediate stage in the manufacturing of two FinFETs. Fins 20 and 22 are adjacent to each other with shallow trench isolation (STI) region 24 therebetween. Gate electrode layer 26 is then blanket formed. Since fins 20 and 22 are higher than STI region 24, gate electrode layer 26 is not flat, and portion 261, which is directly over STI region 24, is lower than portions 262, which are directly over fins 20 and 22.
Referring to FIG. 3, for the patterning of gate electrodes of the respective FinFETs, a substantially flat photoresist 28 is applied. After the patterning, photoresist portions 282 are left over fins 20 and 22 to protect the underlying gate electrode portions 262. Due to the different thicknesses of photoresist 28, which is caused by the topography of the top surface of gate electrode layer 26, it is likely that not all of the undesirable photoresist 28 is removed. Adversely, photoresist portion 281 may be left un-removed. In the subsequent etching of gate electrode layer 26, residue portion 261 of gate electrode layer 26 is adversely not etched. As a result, the gates of the resulting FinFETs may be shorted, causing circuit failure.
What are needed in the art, therefore, are formation methods and structures thereof that incorporate FinFETs to take advantage of the benefits associated with the increased drive currents while at the same time overcoming the deficiencies of the prior art.